MULTI8 Analysis Document




Memory map
$0000-$7fff : ROM / RAM
($6000-$6fff : Disk drive ROM)
$8000-$bfff : RAM / VRAM
$c000-$ffff : RAM

Internal ROM is mapped to $0000-$7fff
When using CP/M, RAM is mapped in reverse
However, when using the disk, the dedicated ROM is mapped at $6000-$6fff

RAM is mapped at $8000-$ffff
However, by changing the bank to V$8000-$bfff VRAM can be mapped



I/O register map
AddressRead/WriteContents
$00R Keycode
The value is retained until another, different key is pressed
$01R

Key status

bit7 : Shift status (1=pressed)
bit6 : Key type (1=function key, 0=other)
bit3 : Current key status (0=pressed)
bit0 : Request receipt of keycode (1=request)

At startup, a diagnostic is carried out for the keycode sub-CPU
At this time, it is required to respond as follows:

inp($01) = 1, inp($00) = 3
inp($01) = 1
inp($01) = 0, inp($00) = ?
$10W Printer data
$14W Printer control
bit0 : Strobe
$18W

AY-3-8912 port number

No.14 is set as an output port

bit3 : Beep (1=on)
bit1 : Cassette relay (1=on)

No.15 is set as an input port, but is unused

$19W AY-3-8912 data (W)
$19R AY-3-8912 data (R)
$1cW HD46505 port number
$1dW HD46505 data
$20R/W 8251 data
Used for playback and recording for the cassette drive
$21R/W 8251 status (R)
8251 control word(W)
$24R/W 8253 counter #0
CLK0 ← 1.9968MHz
GATE0 ← GND
OUT0 → 8251's TXC
$25R/W

8253 counter #1

CLK1 ← 1.9968MHz
GATE1 ← GND
OUT1 → CLK2, IR5 on the 8259

OUT1 outputs on a 1000Hz clock

$26R/W

8253 Counter #2

CLK2 ← OUT1
GATE2 ← GND
OUT2 → IR6 on the 8259

OUT2 outputs on a 1Hz clock
The [time-of-day] clock is driven by interrupt requests from IR6 on the 8259

$27W 8253 control word
$28R/W 8255 port A
Set as an input port
bit7 : unknown
bit6 : existence of kanji ROM (0=exists)
bit5 : VSYNC or HSYNC
bit3 : unknown
bit2 : cassette state (1=currently playing or recording)
bit1 : existence of FDD (0=exists)
bit0 : printer status (1=busy)
$29R/W

8255 port B
Set as an output port

bit7 : colour mode (1=colour, 0=monochrome)
bit6 : number of columns (1=80-column, 0=40-column)
bit3 : $8000-$bfff memory bank state (1=RAM, 0=VRAM)
bit2-0 : displayed graphics page (for monochrome mode)

Operation of the memory bank at $8000-$bfff is actually carried out using $2a
bit3 is a signal to the HD46505 that VRAM access is forbidden?

$2aR/W

8255 port C
Set as an output port

bit5 : $0000-7fff memory bank (1=RAM, 0=ROM)
bit4 : $8000-$bfff memory bank (1=VRAM, 0=RAM)
bit3 : $8000-$bfff VRAM select (0=text)
bit2 : $8000-$bfff VRAM select (0=red)
bit1 : $8000-$bfff VRAM select (0=green)
bit0 : $8000-$bfff VRAM select (0=blue)

When bit4=1, bits 3-0 become valid
When more than one of bits 3-0 are set to 0, writing to multiple screens at the same time is possible

$2bW 8255 control word
$2cR/W 8259 control word #0
IR0 ← uPD765A's TC ON signal
IR5 ← 8253's OUT1
IR6 ← 8253's OUT2
$2dR/W 8259 interrupt mask register (R)
8259 control word #1(W)
$30-$37W Palette definition
When set to all-0, the graphics screen becomes monochrome
$40R/W Lower kanji ROM data (R)
Lower kanji ROM address (W)
$41R/W Upper kanji ROM data (R)
Upper kanji ROM address (W)
$66R Unknown
$70R uPD765A status
$71W uPD765A command
$72R/W uPD765A data
$73R/W

Disk drive status (R)

bit7 : Data ready/Data request (1=Active)
bit0 : Unknown (on standby until it becomes 1)

Disk drive control (W)

bit0 : drive motor (1=on)
$74W Disk drive TC ON (output value optional)
Interrupts come from IR0 on the 8259
$78W Dedicated disk drive ROM
When bit0=1, mapped to $6000-$6fff



The information on this page was personally researched by Takeda.
The accuracy of the contents is not guaranteed.